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Re: Memory copy performance on G5



On Wed, 9 Nov 2005, Qingda Lu wrote:

[...]
> What I want to understand is if half of the ideal bandwidth is the best of
> what I can get.

I suppose 'write allocation' is part of the problem. A typical 'write
back' cache will actually read a cache line from memory on a store
miss, and then modify the cached data. In most situations this is a win,
because the cache line can buffer several writes and only perform a
single memory write later on when the modified cache line is evicted from
the cache.

For pure copying, 'write back' caches are wasteful, though, because the
data they read on store misses will immediately be overwritten in the
cache. Explicit cache control instructions can help here, and some
machines have buffers that try to gather full cache lines worth of stores.
Once a whole cache line has been collected, it can be established in the
cache without a prior read.

  Holger
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References: 
 >Memory copy performance on G5 (From: Qingda Lu <email@hidden>)
 >Re: Memory copy performance on G5 (From: Qingda Lu <email@hidden>)



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