On Tue, 29 Nov 2005, Rustam Muginov wrote:
> I do realize that optimizing code for G3 looks a bit out-of-date, but
> we still considering the ability to run software running on G3.
> I could not find any reference of Apple Dev site. Are they still
> available?
>
The G3 isn't that picky: pipelines are very short by modern standards, and
it is only two way superscalar. Core clock frequencies are comparably low,
hence main memory will appear closer to the processor (in terms of cache
miss latency measured in clock cycles).
Out of order execution capabilities are fairly weak, though, so there is
more of a need to make instruction level parallelism explicit (e.g. by
loop pipelining).
Some G3 models' FPUs have a performance bug that limits throughput to at
most three FP instructions per five cycles. The integer multiplier is not
pipelined, but it has an 'early exit' feature for operands with fewer
significant bits (latency varies from two to six cycles, IIRC).
The G3 is efficient in executing the more complex PowerPC instructions:
bitfield, loads/stores with address update, floating point multiply-add
(the aforementioned performance bug makes the simpler FP instruction
almost as slow as the complex ones). The G3 has a special talent to
execute conditional branches accurately without prediction, if the
condition is set a few cycles before the actual branch.
Unfortunately, the 'dcbt' instruction for prefetching data is implemented
in a peculiar way in the G3: it doesn't actually fetch data into the
cache, but into a special prefetch buffer. So if you want to prefetch more
than a single cache line in advance, you'll immediately evict the
previously prefetched cache line.
That's about all the specialties I can remember.
Holger
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