Re: Merom (Core): Intel's next-generation microarchitecture
- Subject: Re: Merom (Core): Intel's next-generation microarchitecture
- From: Dave Thorup <email@hidden>
- Date: Tue, 18 Apr 2006 10:53:04 -0400
- Delivered-to: email@hidden
- Delivered-to: email@hidden
On Apr 18, 2006, at 10:18 AM, Sanjay Patel wrote:
There's an excellent comparison of the capabilities of both
micro-architectures (along with P4 Prescott) in the linked article
at Real
World Tech:
http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144&p=3
The pictures there clearly show the dispatch and port bottlenecks
of each
implementation.
Is there any word yet on what SSE4 will contain? All I could find in
the realworldtech article was this:
These new SSE4 instructions are not terribly interesting; there
will be some performance gains, but nothing like the improvements
from SSE2.
Even if they aren't "terribly interesting" it would still be nice to
know what those new instructions are.
_____________________________
Dave Thorup
Software Engineer
email@hidden
http://www.kuwan.net
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