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Re: G5s, PCI cache line size & MWI (Memory Write & Invalidate)

Ben,
The AGP and HT host bridges only support up 64 byte transactions. At least from the processor this means that access to AGP and HT must be cache inhibited since 128 byte requests will fail. I'm guessing that the 128 byte MWI requests to memory are failing for the same reason. You will probably need to leave the PCI devices cache line size at 64 bytes.
Josh


At 6:25 PM +1100 11/16/03, Benjamin Herrenschmidt wrote:
On Sun, 2003-11-16 at 15:42, Benjamin Herrenschmidt wrote:
Hi !

OOps, looks like the beginning of my message got truncated some
way...

So the question is, what is the meaning/usefulness of the cache
line size register and the MWI bit ...

... in PCI command register) in a G5 ? According to HT specs, they don't
make much sense at all it seems, though I suppose anything hooked
to the AGP slot and doing PCI cycles to memory may need a 128 bytes
cache line size if doing MWI, right ?

I'm asking because I had some problems with the GEM (GMAC) chip
corrupting memory around destination buffers when setting its
cache line size to 128 bytes (even when MWI bit isn't set), which
is very weird (in Linux btw ;-), and I noticed OF sets all sort of cache
lines sizes at boot on devices & HT<->PCI bridges, in a way
which seem a bit "random" to me (mostly 0x10 though, which means
64 bytes, so half of the CPU cache line size)

It may just be a specific problem to that part though, but I felt
it may be worth clarifying the general requirements may be of interest
to people doing PCI devices for MacOS X as well, so I'm raising the
issue on this list.

Regards,
Ben.
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References: 
 >G5s, PCI cache line size & MWI (Memory Write & Invalidate) (From: Benjamin Herrenschmidt <email@hidden>)
 >Re: G5s, PCI cache line size & MWI (Memory Write & Invalidate) (From: Benjamin Herrenschmidt <email@hidden>)



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