which mentions msync. But gcc doesn't know msync! It even says that
msync is a replacement for sync
Is that sync 2, or something else?
Something else. They have msync and mbar.
Can I use isync or even eieio instead? Is there a way to put msync
into the assembler?
You can sometimes use light-weight sync 1 "lwsync" on G5-MP's, which
allows loads to happen speculatively across the barrier **, but you
probably need to leave the full sync instruction in there for
G4-MP's... that's why the instruction exists: to ensure that
modifications to a shared data structure (memory) is forced to a known
state with respect to all other processors and concerned mechanisms in
the system.
Crap. Is there a way with defines to do this; i.e., tell a G5 (power4 >
models) from lesser powerpcs?
On a G3/G4/G5 uni-processor machine, it can often be eliminated. On
MP hardware, no way. If you can make it work for you, I'd suggest
using an atomic lwarx/stwcx operation. You might be able to
substitute eieio, depending on what you're doing immediately after
releasing the lock.
My general philosophy about barriers:
use sync between a write and a dependent read
use isync after a test, prior to subsequent reads
otherwise use lwsync **
On second thought, the IBM doc does give code for locking and unlocking
using lwarx/stwcx (which use isync). I might just do this.
BTW, the commpage spinlock jumptable primitives are set to use the
most optimal lock implementation for the current hardware. Maybe you
can call into those instead?
