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Re: SSE3.5, SSE4
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Re: SSE3.5, SSE4



On Sep 28, 2006, at 6:37 AM, Holger Bettag wrote:

Intel aqcuires a broader understanding of the importance of SIMD:

ftp://download.intel.com/technology/architecture/new-instructions- paper.pdf

A few small steps into the right direction, plus one big step into a new
field of vectorized string processing.

So we'll get back our vec_sel (yeah!), vec_min, vec_max, plus a new test-and-set instruction which will facilitate atomic bitfield operations (ie cmpxchg16b using XMM), float dot product!!!, 32x32->64 bit mult, and lots of packed GPR<->XMM manipulations that will ease the lack of a permute unit.


Where's the "new" register file described? No need to add more GPR's, but hopefully they'll increase XMM to 32 (or more) registers. It would be nice even if there were the same 16 XMM for use as src/ dest with any instruction, plus 16 to 48 CXMM registers to hold constant values, ie src-only, with special MOV inst's to set their values. Better yet just give us 64 XMM's. ;)
--
Shaun Wexler
MacFOH
http://www.macfoh.com



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References: 
 >Meaning of letters in simg5 output (From: Jonathan Taylor <email@hidden>)
 >SSE3.5, SSE4 (From: Holger Bettag <email@hidden>)



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