site_archiver@lists.apple.com Delivered-To: Darwin-dev@lists.apple.com Dear Josh, Thank you very much for this information. I have an additional question that parallels the use of the cycle counter on later Intel and compatible microprocessos. Looking at the various PowerPC architecture manuals on the later chip versions there are some performance monitor counter registers like PMC1, etc. The event to monitor is set in the MMCR0 register and it can be the number of processor cycles. Several observations are immediate. It is only 32 bits, interrupts on overflow and to set the registers requires supervisor mode. Has Apple ever investigated trying to provide an interface to this feature to get even better timing resolution then the time base register method? If yes, what were the lessons? If no, why not? Sincerely, Martin Knapp-Cordes

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Martin,

At 12:13 PM -0400 10/28/04, Martin Knapp-Cordes wrote:

...

Hi,

I am a developer at The MathWorks working on improving the precision and accuracy of our tic/toc functions in the MATLAB language. These functions are used for measuring elapsed wallclock time for for one or more operations in the MATLAB language.

I am planning to use the following API to do elapsed timing:

mach_absolute_time() mach_timebase_info()

I have confirmed in my code so far that indeed on G5 desktops the update frequency is about 33MHz, and appears to be fixed.

The frequency will always be fixed on a given system. sysctlbyname's hw.tbfrequency will give you the most accurate value known for the frequency.

...

I have been looking at the Timer Facilities (Chapter 8) in Book E: Enhanced PowerPC Architecture published by IBM which is very interesting.

Can anyone answer the following questions?

1. What clock mechanism (hardware/software) is driving the update of that register for Apple systems? What/who makes the decision that say on a G5 it is 33 MHz?

On all G5 systems, the Time Base is driven off of an external 33 MHz clock. On older G4 system, the TB frequency is 1/4 of the bus frequency. On newer G4 systems, where the bus frequency could change, it is driven from an external clock at 18.432 MHz.

...

2. Is the update frequency constant on all Apple systems, or can it vary? We got burned recently on the Pentium M processor on Windows trying to use the CPU cycle counter. It is clearly not constant for those systems. Fortunately, Microsoft does provide an API that handles this problem. Are we going to run into a problem on say some Apple laptops where that interface above will not work?

Since all of the Kernel's timing is based on this clock, we require that it run at a fixed frequency.

...

Any help which be much appreciated.

Sincerely, Martin Knapp-Cordes

--------------------------------------------------------------- | Martin Knapp-Cordes martin@mathworks.com | | The MathWorks, Inc. http://www.mathworks.com | | 3 Apple Hill Drive Natick, MA 01760 | | Tel: (508) 647-7321 Fax: (508) 647-7015 | ---------------------------------------------------------------

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