Hi ! While looking at the Heathrow.cpp code to compare with what I'm doing in Linux (chasing a lost interrupt problem with the PMU that occurs occasionally), I found something weird in the Darwin implementation. It defines interrupts matching the mask 0x1ff00000 of the first register set (the one at macio_base + 0x2n) as beeing level interrupts, all others (including the second register set at + 0x1n) as beeing edge interrupts. The result is that level interrupts end up beeing interrupt number 20 to 28, all other beeing edge triggered. Are you sure this is right ? That gives on a wallstreet the NMI & cascade (second heathrow) beeing edge (while the NMI is specifically level triggered on openpic machines and that makes more sense to have it level triggered), while all others beeing edge (especially IDE disk interrupts which are usually known to be level interrupts as the disk assert them until the status register is read) There's also a typo in the code for handling lost interrupts which uses the first level register in the code for checking the second register set (I just posted a bug report about this). Finally, the code og getVectorType() is confusing. It should probably test the vector is in the range of the first register set before doing (1 << vectorNumber) for completeness. The current code works as long as (1 << X) with X >= 32 returns 0 but I did see compilers optimizing this badly, so I feel this is dangerous coding. Regards, Ben.