site_archiver@lists.apple.com Delivered-To: darwin-kernel@lists.apple.com Victor On Nov 26, 2007, at 8:57 AM, Michael Smith wrote: On Nov 25, 2007, at 11:29 PM, Victor Vedovato wrote: = Mike _______________________________________________ Do not post admin requests to the list. They will be ignored. Darwin-kernel mailing list (Darwin-kernel@lists.apple.com) Help/Unsubscribe/Update your Subscription: http://lists.apple.com/mailman/options/darwin-kernel/site_archiver%40lists.a... On x86, I believe the MTRR/PAT registers are the final say (over MMU PTEs) as to the read/write/allocation/eviction policy for CPU caches on system memory. We're concerned about these since we need to coordinate the CPU cache policy with GPU cache policy - flushing is a really bad strategy to mitigate these issues. We need a holistic view of CPU, GPU, System and GPU memory caching policy - reggie_se is a good start for this. Derek - thanks for the excellent response. We can use reggie_se to set/reset the registers for debugging. It's not clear from others that OS X uses the MTRRs/PATs for cache control. Can you confirm that? Thanks again. If you were to describe what you meant by "cache control", you might be able to get a clearer answer. This email sent to site_archiver@lists.apple.com