Re: Problem on dual-processor Macs
Re: Problem on dual-processor Macs
- Subject: Re: Problem on dual-processor Macs
- From: Wade Tregaskis <email@hidden>
- Date: Fri, 26 Sep 2003 00:24:57 +1000
These indexes are C 'int' data types, so are signed 32-bit
integers at the CPU instruction level. I would expect that
incrementing a 32-bit integer to be an atomic operation,
... And you would be mistaken. :-) While the PPC ISA no doubt has an
operation (or sequence of operations) that accomplishes an "atomic
increment", your C compiler is not going to generate code for ++i (or
any variation thereof) that uses it.
If you grab a copy of the Programming Environments Manual (for 32-bit
implementations of the PPC architecture*) you can find the relevant
instructions and references in the following locations:
* Section 4, page 51, heading "4.2.6 Memory Synchronization
Instructions". This covers the lwarx and stwcx. instructions, which
can be used for the type of basic semaphore operation you seem to be
asking for
* Appendix E - "Synchronization Programming Examples", specifically
sections 2 and 4
You can get the PEM sent to you from Motorola completely free of
charge, which is fantastic if you're a budding PPC assembly programmer
(you can also get several complementary references for specific
architectures, e.g. 7410/7400, 7450, 750, etc).
Wade Tregaskis
-- Sed quis custodiet ipsos custodes?
* = That's what I have handy, anyway. This particular one came from
Motorola, so obviously they're not going to produce anything relevant
to the G5. IBM also produce a PEM, which is probably pretty much the
same as Motorola's for the 32-bit version, but IBM won't send you out a
copy [for free].
_______________________________________________
cocoa-dev mailing list | email@hidden
Help/Unsubscribe/Archives:
http://www.lists.apple.com/mailman/listinfo/cocoa-dev
Do not post admin requests to the list. They will be ignored.