Re: (HAL) clock sources
Re: (HAL) clock sources
- Subject: Re: (HAL) clock sources
- From: "B.J. Buchalter" <email@hidden>
- Date: Wed, 02 Oct 2002 17:13:32 -0400
on 10/2/02 5:07 PM, Matthew Xavier Mora at email@hidden wrote:
>
At 3:13 PM -0400 10/2/02, B.J. Buchalter wrote:
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> on 10/2/02 2:33 PM, Jeff Moore at email@hidden wrote:
>
>
>
>>
>
>> I would not make that assumption. While it may seem odd at first
>
>> glance, but you don't want to tie your hands with respect to what
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>> future hardware may be capable of.
>
>>
>
>> On the other hand, a piece of hardware that did have individual clock
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>> controls on a stream would be a pretty exotic piece of gear.
>
>
>
> Well the obvious place would be a ASRC device that can clock its input and
>
> output from different sources. So I can see a use -- but I guess that the
>
> real question is if this is really a "clock source" in the CA sense -- or
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> does it really require a different type of control? I was under the
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> impression that by definition an Audio Engine has one shared clock -- if a
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> stream has a different clock (at least by the time it has hit the computer)
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> it should be in a different engine.
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>
>
> Opinions?
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>
>
I think you are right B.J. I quote from the header doc:
>
>
" Within a single IOAudioEngine, all sample
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* buffers must be the same size and be running at the same sample
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rate. If different buffers/streams can
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* be run at different rates, separate IOAudioEngines should be
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used. The IOAudioEngine subclass must
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* also call setSampleRate() at init time to indicate the starting
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sample rate of the device.
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*
>
"
>
>
mLAN poses an interesting dilemma here as there is no reason why an
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mLAN device shouldn't be able to receive audio on multiple isoch
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channels at different rates (I don't think the Mac OS 9 code allows
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that). I guess in that case there would have to be an audio engine
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created for each different sample rate coming in to the one device.
Right, exactly. On related note, do any mLan implementations actually
support multiple s/r in one (physical) device? Obviously a host
implementation could/should/has to, but does anyone's -6 silicon support
multiple clock recovery in the same chip?
Best regards,
B.J. Buchalter
Metric Halo
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