Re: Pinning IO Thread to a particular processor
Re: Pinning IO Thread to a particular processor
- Subject: Re: Pinning IO Thread to a particular processor
- From: Shaun Wexler <email@hidden>
- Date: Mon, 30 Jan 2006 15:21:33 -0800
On Jan 30, 2006, at 11:41 AM, Jeff Moore wrote:
I don't know that the scheduler has a notion of processor affinity.
Even if it did, the HAL owns the thread and as such it can come and
go ou from under you.
At any rate, while bouncing around between processors can cause
caches thrash a bit more often, there isn't exactly a whole lot of
cache on a G5 anyway. So the effect wouldn't be as pronounced.
Besides, when you pin a thread to a particular processor, you are
trading cache coherency for increased scheduling latency. As the IO
buffer size gets smaller, the scheduling latency, which is
generally always the same, will take an increasing amount of the
available time. So, I'm not sure that the trade off would actually
result in better performance.
Another issue the Quad might be susceptible to could be related to
the shared 2MB cache of each dual-core chip. It's possible that a
thread running on "Core B" could evict data from "Core A's" cache,
forcing its HAL thread to stumble out to main memory for every bit.
Worst-case scenario, it might also be paging, blocking the IOProc.
Maybe he's not wired-down when/where he needs to be? ;)
--
Shaun Wexler
MacFOH
http://www.macfoh.com
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