Re: cache clearing from keeping code and data in the same segment
Re: cache clearing from keeping code and data in the same segment
- Subject: Re: cache clearing from keeping code and data in the same segment
- From: Jonas Maebe <email@hidden>
- Date: Mon, 19 Jan 2009 13:25:14 +0100
On 19 Jan 2009, at 11:36, Joel Reymont wrote:
Keeping code and data in the same segment apparently results in the
clearing of the instruction cache on every data access.
I very much doubt that. Why do you think that is the case?
Keeping code and read/write data close to each other (putting them in
the same segment may qualify) may result in the icache getting
invalidated on data writes (to deal with self-modifying code), but I
can't imagine how or why memory reads would result in icache
invalidations (read-only data is common in code segments on many
platforms). Such flushing, if any, would performed by the cpu though,
the OS has no influence over that.
Note that this would most likely be x86-specific. On e.g. the PPC you
have to manually invalidate the icache when using self-modifying code.
Also note that in general it's a bad idea to put code and data close
to each other (even if no automatic flushing whatsoever happens),
because it pollutes both the icache and dcache: the icache will partly
contain data (which is never fetched from the icache) and the data
cache will partly contain instructions (which are never fetched from
the dcache), thereby reducing the effectiveness of both.
Jonas
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