Re: Darwin & SMT?
Re: Darwin & SMT?
- Subject: Re: Darwin & SMT?
- From: Niall Dalton <email@hidden>
- Date: Thu, 12 Sep 2002 17:57:42 -0700 (PDT)
On Wed, 11 Sep 2002, Bernie Zenis wrote:
>
As far as I am aware, there has been no work done on the possibility of
>
removing speculative instruction execution, out of order instruction
>
execution, nor branch prediction in SMT processors. Some/All of those
There has been some work comparing an in-order and out-of-order
SMT processors:
S. Hily, A. Seznec `` Out-Of-Order Execution May Not Be Cost-Effective on
Processors Featuring Simultaneous Multithreading '', IRISA Report No 1179,
March 1998, short version appears in proceedings of HPCA-5, Orlando,
Jan. 1999.
The report is available from
http://www.irisa.fr/caps/PROJECTS/Architecture/CacheArchitecture_US.html#SECTION04
It comes down to the fact that if you are going for maximum throughput
and ready threads are available, then an in-order SMT gives almost
the same performance as an out-of-order SMT.
>
Last I heard, the SMT simulator is still Alpha only. Anyone been working
>
on a PowerPC version?
SMTSIM is still Alpha only afaik. One other simulator worth checking out
is James Burns' (ex-USC, now with Intel) simulator that allows one to
explore the tradeoffs between SMT, chip-multiprocessor (CMP) and a mixed
SMT/CMP. It is based on SimpleScalar, which now also has a PowerPC
frontend. It may be possible, with sufficiently motivated hacking, to
come up with some version combining those..
I would assume that IBM's internal simulator - which _may_ be
available for academic usage - can simulate SMT PowerPC as this is due
for Power 5 I believe.
Regards,
niall
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