Re: Questions about debugging kernel panics
Re: Questions about debugging kernel panics
- Subject: Re: Questions about debugging kernel panics
- From: William Kucharski <email@hidden>
- Date: Tue, 17 Jan 2006 15:07:39 -0700
On Tuesday, January 17, 2006, at 02:38PM, James Reynolds <email@hidden> wrote:
What, precisely are you trying to figure out?
This particular panic was, as it states, due to an alignment error.
The instruction in question is likely trying to do a word-aligned operation and the
address it's trying to read from, 0x1bcbeae, certainly isn't word-aligned.
For example, the MPC7450 user's manual gives these possible causes:
* The operand of a floating-point load or store is not word-aligned.
* The operand of lmw, stmw, lwarx, or stwcx. is not word-aligned.
* The operand of dcbz is in a page that is write-through or cache-inhibited.
* An attempt is made to execute dcbz when the data cache is disabled or
locked.
* An eciwx or ecowx is not word-aligned
* A multiple or string access is attempted with MSR[LE] set
* In 60x bus mode, an access caused by stvx, stvxl, lvx, or lvxl
instruction to a cache-inhibited page, write-through page, disabled L1
cache, or if all ways of the cache are locked.
* In 60x bus mode, an access caused by cache-inhibited AltiVec loads,
stores, and write-through stores. The 60x bus mode does not support
16-byte bus transactions. Note this requires a re-write of the alignment
exception routines in software that supports AltiVec quad-word access in
60x bus mode on the MPC7450.
Similar causes would apply to other PPC CPUs.
The question then becomes WHY the code in question is trying to operate on an unaligned
address, and it's usually either because of a software error or because something has stomped
on the memory location or register that contained the address.
William Kucharski
email@hidden
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