A few low-level GDT/LDT K64 questions
A few low-level GDT/LDT K64 questions
- Subject: A few low-level GDT/LDT K64 questions
- From: Ben Gertzfield <email@hidden>
- Date: Wed, 16 Sep 2009 15:58:06 -0700
Hi folks,
Now that K64 is out there, we ran into a few interesting low-level
questions about how the K64 (and K32) kernels handle the GDT and the
LDT.
These questions are in the context of a thread that's entered a K64
kernel extension via an ioctl. We ran into a few differences in the
way the %fs and %gs registers are treated in K64, so we wanted to make
sure we understood the expectations the kernel has with regards to the
GDT and the LDT and these registers.
1. Is there an expectation within the kernel that the in-memory
descriptor tables will be synchronized with the descriptor cache?
That is, if the GDT or LDT is modified, can the descriptor cache
hold stale values (beyond the local scope of the GDT/LDT
modification)?
2. Is there an expectation within the kernel that the selector indices
for all segment registers will always be within the bounds of the
referenced descriptor table?
That is, if the GDT or LDT shrinks in size, can a segment register
hold a stale value that is now out of bounds for the referenced
descriptor table (beyond the local scope of the GDT/LDT modification)?
3. In general, can the following sequence expected to be idempotent
with respect to the %fs descriptor cache:
mov $IA32_FS_BASE, ìx
rdmsr
mov %fs, %bx
mov %bx, %fs
wrmsr
Thanks so much,
Ben
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