Re: Memory barriers & the kernel
Re: Memory barriers & the kernel
- Subject: Re: Memory barriers & the kernel
- From: Dave Keck <email@hidden>
- Date: Wed, 3 Mar 2010 19:42:57 -1000
After further digging, I believe I've found the answers to my
questions. I'm documenting my findings here for the sake of the
archives.
1. The kernel's mutex facilities do indeed include memory barriers (at
least the one I've looked at anyway - lck_mtx_t.) The implementation
of lck_mtx_lock() can be seen here:
http://opensource.apple.com/source/xnu/xnu-1456.1.26/osfmk/i386/i386_lock.s
The core mechanism is the lock/cmpxchg instruction. As stated by
Intel's 64 and IA-32 Architectures Software Developer’s Manual, Volume
3A, section 8.1.2.2
(http://www.intel.com/Assets/PDF/manual/253668.pdf):
"Locked instructions can be used to synchronize data written by
one processor and read
by another processor. For the P6 family processors, locked
operations serialize all
outstanding load and store operations (that is, wait for them to
complete)."
2. The OSAtomic functions in kernel-space also include a barrier,
which is mentioned in the 10.6 version of OSAtomic.h. (I was reading
the 10.5 header in my original email.) The kernel-space atomic
functions are defined here:
http://opensource.apple.com/source/xnu/xnu-1456.1.26/libkern/i386/OSAtomic.s
Note the lock/cmpxchgl CAS instructions. Furthermore, I found that
both the barrier and non-barrier OSAtomic functions in user-space
actually both use a barrier. The user-space atomic functions are
defined here:
http://opensource.apple.com/source/Libc/Libc-583/i386/sys/OSAtomic.s
(Note the DECLARE macro at the beginning, which is the mechanism for
combining the barrier and non-barrier versions of the various atomic
functions.) This file references functions in the commpage:
http://opensource.apple.com/source/xnu/xnu-1456.1.26/osfmk/i386/commpage/atomic.s
... and once again we find our lock/cmpxchgl.
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