Re: Compiler optimization doing strange things
Re: Compiler optimization doing strange things
- Subject: Re: Compiler optimization doing strange things
- From: "Jan E. Schotsman" <email@hidden>
- Date: Mon, 15 May 2006 11:58:35 +0200
On 15-mei-06, at 10:56, Steve Checkoway wrote:
I'm seeing some very strange interactions with altivec and compiler
optimizations that I'm hoping someone can explain to me. The basic
algorithm I'm writing is:
[...]
Three questions:
1. Why does the compiler not do loop unrolling when I use size & ~0x7?
Dunno. Ask on the Altivec list.
2. When the compiler does unroll the loop why does it not interleave
the independent instructions?
I have seen this with CodeWarrior too. When I switched on 'loop
unrolling' it just repeated the loops without rescheduling. If the
processor can reschedule on the fly to some extent this may still be
beneficial.
3. Is there perhaps a better way to write this algorithm to eliminate
these stalls?
On the G4 you can use the __dcbt cache hint to prevent load stalls. On
the G5 prefetching is automatic as long as you make sure your memory
accesses are sequential.
I don't think you need to make any smart changes to the non-load part
of the code because a simple calculation like this is probably limited
by memory access speed anyway.
Jan E.
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