Re: I/O Latency
Re: I/O Latency
- Subject: Re: I/O Latency
- From: Dennis Gunn <email@hidden>
- Date: Sat, 16 Oct 2004 18:17:18 +0900
On Oct 15, 2004, at 8:37 AM, William Stewart wrote:
We believe that it is possible with certain architectures for the DMA transfer to be minimal (a few samples). With good timing models, the TS Resolution can be within a single sample. So, it should be possible to have a combined “safety offset” in the single digit sample range.
We’d like to understand the problems that arise for a driver to achieve this kind of figure and to fix them.
Could this be applicable to the apple internal hardware in a G5?
With logic's buffers set to 64samples using the convertors of my multiface through the Apple's digital inputs I measure a total monitoring latency of 442 samples.
Which is pretty mysteriously higher than the latency you get if you just use the RME driver which is - 322 samples
Is there something special going on in the G% HW or is there some way that it could be a proving ground for a lower latency driver?
OS 9 (ASIO):
Logic 6.1.0 monitoring latency - 192 samples
<x-tad-bigger>XP2000, Win2k, Athlon
@44.1khz with the logic sample buffer at 64 total monitoring latency = 190 samples
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