Re: I/O Latency
Re: I/O Latency
- Subject: Re: I/O Latency
- From: Dennis Gunn <email@hidden>
- Date: Fri, 15 Oct 2004 23:55:45 +0900
On Oct 15, 2004, at 8:37 AM, William Stewart wrote:
Thanks for all of the comments – I’m not quoting any of these as this might be a longish email...
I want to make it clear to everyone that we care a great deal about this area and have (and will) spend time on getting this right.
<snip>
We believe that it is possible with certain architectures for the DMA transfer to be minimal (a few samples). With good timing models, the TS Resolution can be within a single sample. So, it should be possible to have a combined “safety offset” in the single digit sample range.
We’d like to understand the problems that arise for a driver to achieve this kind of figure and to fix them.
I can't tell you what a huge relief these comments are.
Thank you who have contributed to this thread so much for the clarification of what was going on.
This has been extremely educational for me and I am really happy to see that there is some hope of a resolution the idea that a dedicated logic/Mac user like me might have to take his stinking PC out of mothballs and start dealing with all those various Windows type problems just to get around the latency issue was really getting me down.
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