Re: Native Device Formats
Re: Native Device Formats
- Subject: Re: Native Device Formats
- From: email@hidden
- Date: 09 Jun 2008 14:45:54 +0100
I agree with your statement that that's how it can come over, though in
that example so long as the signal persists for sufficient time (more than
a millisecond or so since 24-23 = 1kHz) sufficient information will have
been gathered to meet the Sampling Theory criteria. However, this actually
doesn't affect my point - the precise sub multiple example I used was
purely there to make it simple to visualise the process, and it is true in
the more general (non-locked) case, too. See, for instance,
http://www.tcelectronic.com/media/nielsen_lund_2003_overload.pdf for more
details.
Dave
On Jun 9 2008, Mikael Hakman wrote:
If you start sampling e.g. 23 kHz sine wave with 48 kHz SR at an
unfortunate time, you will have a large number of very small positive and
negative values slowly increasing. Only after many cycles the sample time
will coincide with actual peak or low. If this signal ceases before the
sample values reach any significant "height", and you then scale up the
digital values (because the signal is so low), then no headroom in the
world will help you. Therefore you should attenuate/amplify your signal
before ADC in such a way that the actual (not the sampled) peaks and lows
are below FS (and some headroom). Then, whether your ADC gets samples
exactly at these peaks and lows, or not, will be immaterial. Providing
this sampled signal to a DAC will then reproduce the original wave.
On Monday, June 09, 2008 10:56 AM, Dave Malham wrote:
Then, of course, there's the whole hairy question of intersample
"digital overs" where a signal re-constructed from a stream of digital
words can have positive peaks higher (or negative peaks lower) than the
steady state levels the digital words can represent (or the DAC they are
sent to can reproduce). If this seems odd, think of a max level sine
wave at an odd sub-multiple of the sample rate. Under these
circumstances it is possible for the sample points to fall either side
of the peaks of the sine wave, rather than on them, so the peak of the
sine wave will be implicitly, rather than explicitly, represented and
can, in fact, actually be over 0dBFs. This doesn't matter if all you are
doing is storing the signal**, but as soon as you do any processing in
the time/frequency domain it can pop up and bite you.
Dave
**It shouldn't really cause you any problems going to analog, so long as
the designer has done the proper, professional thing and allowed some
headroom in the analog part of the circuit - but that doesn't always
happen. :-(
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