page tables in dual and quad G5 systems?
page tables in dual and quad G5 systems?
- Subject: page tables in dual and quad G5 systems?
- From: Parav Pandit <email@hidden>
- Date: Wed, 19 Jul 2006 05:56:53 +0100 (BST)
Hi,
In our xnu kernel, for dual and quad SMP system, do we
have individual page table for each processor in the
memory?
I guess so.
First the process starts on processor 1 and than if it
gets schedule on processor 2 later on, there will be
page table update through the page fault.
Is that correct understanding?
Regards,
Parav Pandit
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