Re: page tables in dual and quad G5 systems?
Re: page tables in dual and quad G5 systems?
- Subject: Re: page tables in dual and quad G5 systems?
- From: Michael Smith <email@hidden>
- Date: Thu, 20 Jul 2006 01:42:00 -0700
On Jul 18, 2006, at 9:56 PM, Parav Pandit wrote:
In our xnu kernel, for dual and quad SMP system, do we
have individual page table for each processor in the
memory?
I guess so.
I would encourage you to check out Amit Singh's new book.
First the process starts on processor 1 and than if it
gets schedule on processor 2 later on, there will be
page table update through the page fault.
Is that correct understanding?
For each active address space, there is necessarily a set of
mappings available between virtual and physical addresses.
PPC mappings are not particularly like the intel/VAX/etc. style
mappings that it sounds like you're familiar with.
Are you asking out of curiosity, or is there something specific you
are looking for?
= Mike
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