Re: page tables in dual and quad G5 systems?
Re: page tables in dual and quad G5 systems?
- Subject: Re: page tables in dual and quad G5 systems?
- From: Steve Checkoway <email@hidden>
- Date: Wed, 19 Jul 2006 13:42:53 -0700
On Jul 18, 2006, at 9:56 PM, Parav Pandit wrote:
Hi,
In our xnu kernel, for dual and quad SMP system, do we
have individual page table for each processor in the
memory?
I guess so.
First the process starts on processor 1 and than if it
gets schedule on processor 2 later on, there will be
page table update through the page fault.
Is that correct understanding?
I can't imagine that would be the case. You'd need two (or four) page
tables which would seem to be unnecessary. I think each processor has
its own TLB and when the processes get scheduled on a different
processor, you'll get a TLB miss but you shouldn't get a page fault.
(After all, the pages are still in memory, it's not like they need to
be brought in from the disk.)
--
Steve Checkoway
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